mirror of https://github.com/YosysHQ/yosys.git
8 lines
190 B
Plaintext
8 lines
190 B
Plaintext
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logger -expect error "Cannot add signal `\\x' because a memory with the same name was already created" 1
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read_verilog <<EOT
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module top;
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reg [2:0] x [0:0];
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reg [2:0] x;
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endmodule
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EOT
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