mirror of https://github.com/YosysHQ/yosys.git
9 lines
209 B
Plaintext
9 lines
209 B
Plaintext
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logger -expect error "Cannot add pwire `\\x' because a signal with the same name was already created" 1
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read_verilog -pwires <<EOT
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module top;
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wire x;
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assign x = 1;
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localparam x = 2;
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endmodule
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EOT
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