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12 lines
206 B
Systemverilog
12 lines
206 B
Systemverilog
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module top(input clk, input signed [3:0] sel_w , output reg out);
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always @ (posedge clk)
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begin
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case (sel_w) inside
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[-4:3] : out <= 1'b1;
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[4:5] : out <= 1'b0;
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endcase
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end
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endmodule
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