mirror of https://github.com/YosysHQ/yosys.git
42 lines
884 B
Plaintext
42 lines
884 B
Plaintext
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verific -sv -lib +/quicklogic/qlf_k6n10f/dsp_sim.v
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verific -sv <<EOF
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module top (
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input wire [19:0] a,
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input wire [17:0] b,
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output wire [37:0] z,
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input wire clk,
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input wire reset,
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input wire unsigned_a,
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input wire unsigned_b,
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input wire f_mode,
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input wire [2:0] output_select,
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input wire register_inputs
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);
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// module instantiation
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QL_DSP2_MULT_REGIN_REGOUT #(
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.MODE_BITS(80'h1232324)
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) u1 (
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.a (a),
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.b (b),
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.z (z),
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.clk (clk),
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.reset (reset),
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.unsigned_a (unsigned_a),
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.unsigned_b (unsigned_b),
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.f_mode (f_mode),
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.output_select (output_select),
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.register_inputs (register_inputs)
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);
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endmodule
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EOF
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verific -import top
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hierarchy -top top
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synth_quicklogic -family qlf_k6n10f
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select -assert-count 1 t:QL_DSP2_MULT_REGIN_REGOUT a:MODE_BITS=80'h1232324
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