mirror of https://github.com/YosysHQ/yosys.git
22 lines
473 B
Plaintext
22 lines
473 B
Plaintext
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read_verilog << EOT
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module test(input [7:0] a, b, c, d, output [7:0] x, y, z);
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assign x = a + b, y = b + c, z = c + d;
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endmodule
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EOT
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copy test gold
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rename test gate
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submod -name mycell gate/x %ci*
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design -copy-to mymap mycell
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extract -map %mymap gate
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select -assert-count 3 gold/t:*
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select -assert-count 3 gold/t:$add
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select -assert-count 3 gate/t:*
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select -assert-count 3 gate/t:mycell
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miter -equiv -flatten gold gate miter
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sat -verify -prove trigger 0 miter
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