mirror of https://github.com/YosysHQ/yosys.git
29 lines
497 B
Plaintext
29 lines
497 B
Plaintext
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# SV LRM A2.2.1
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read_verilog -sv <<EOT
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module test_signed();
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parameter integer signed a = 0;
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parameter integer unsigned b = 0;
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endmodule
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EOT
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design -reset
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read_verilog -sv <<EOT
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module test_signed();
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parameter logic signed [7:0] a = 0;
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parameter logic unsigned [7:0] b = 0;
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endmodule
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EOT
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design -reset
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logger -expect error "syntax error, unexpected TOK_INTEGER" 1
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read_verilog -sv <<EOT
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module test_signed();
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parameter signed integer a = 0;
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parameter unsigned integer b = 0;
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endmodule
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EOT
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