mirror of https://github.com/YosysHQ/yosys.git
110 lines
3.6 KiB
Plaintext
110 lines
3.6 KiB
Plaintext
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read_verilog <<EOT
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(* module_attr = "module_attr" *)
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module some_mod(input a, output y);
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assign y = a;
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endmodule
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module top(input a, output y);
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(* inst_attr = "inst_attr" *)
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some_mod some_inst(.a(a), .y(y));
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endmodule
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EOT
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hierarchy -top top
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flatten
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select -assert-count 1 top/n:some_inst top/t:$scopeinfo %i
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select -assert-count 1 top/n:some_inst top/r:TYPE=module %i
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select -assert-count 1 top/n:some_inst top/a:cell_inst_attr=inst_attr %i
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select -assert-count 1 top/n:some_inst top/a:module_module_attr=module_attr %i
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select -assert-count 1 top/n:some_inst top/a:cell_src %i
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select -assert-count 1 top/n:some_inst top/a:module_src %i
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opt_clean
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select -assert-count 1 top/t:$scopeinfo
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opt_clean -purge
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select -assert-count 0 top/t:$scopeinfo
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design -reset
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read_verilog <<EOT
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(* module_attr = "module_attr_deep" *)
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module some_mod_deep(input a, output y);
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assign y = a;
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endmodule
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(* module_attr = "module_attr" *)
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module some_mod(input a, output y);
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(* inst_attr = "inst_attr_deep" *)
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some_mod_deep some_inst_deep(.a(a), .y(y));
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endmodule
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module top(input a, output y);
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(* inst_attr = "inst_attr" *)
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some_mod some_inst(.a(a), .y(y));
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endmodule
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EOT
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hierarchy -top top
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flatten
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select -assert-count 2 top/t:$scopeinfo
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select -assert-count 1 top/n:some_inst top/t:$scopeinfo %i
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select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep
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select -assert-count 1 top/n:some_inst top/r:TYPE=module %i
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select -assert-count 1 top/n:some_inst top/a:cell_inst_attr=inst_attr %i
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select -assert-count 1 top/n:some_inst top/a:module_module_attr=module_attr %i
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select -assert-count 1 top/n:some_inst top/a:cell_src %i
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select -assert-count 1 top/n:some_inst top/a:module_src %i
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select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/r:TYPE=module %i
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select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/a:cell_inst_attr=inst_attr_deep %i
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select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/a:module_module_attr=module_attr_deep %i
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select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/a:cell_src %i
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select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/a:module_src %i
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design -reset
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read_verilog <<EOT
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(* module_attr = "module_attr_deep" *)
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(* keep_hierarchy *)
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module some_mod_deep(input a, output y);
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assign y = a;
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endmodule
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(* module_attr = "module_attr" *)
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module some_mod(input a, output y);
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(* inst_attr = "inst_attr_deep" *)
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some_mod_deep some_inst_deep(.a(a), .y(y));
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endmodule
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module top(input a, output y);
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(* inst_attr = "inst_attr" *)
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some_mod some_inst(.a(a), .y(y));
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endmodule
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EOT
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hierarchy -top top
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flatten top
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select -assert-count 1 top/t:$scopeinfo
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setattr -mod -unset keep_hierarchy *
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flatten
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select -assert-count 2 top/t:$scopeinfo
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select -assert-count 1 top/n:some_inst top/t:$scopeinfo %i
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select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep
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select -assert-count 1 top/n:some_inst top/r:TYPE=module %i
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select -assert-count 1 top/n:some_inst top/a:cell_inst_attr=inst_attr %i
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select -assert-count 1 top/n:some_inst top/a:module_module_attr=module_attr %i
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select -assert-count 1 top/n:some_inst top/a:cell_src %i
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select -assert-count 1 top/n:some_inst top/a:module_src %i
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select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/r:TYPE=module %i
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select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/a:cell_inst_attr=inst_attr_deep %i
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select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/a:module_module_attr=module_attr_deep %i
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select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/a:cell_src %i
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select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/a:module_src %i
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