2019-08-21 15:36:01 -05:00
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read_verilog <<EOT
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module top;
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parameter DATADEPTH=2;
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parameter DATAWIDTH=1;
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(* keep, nomem2reg *) reg [DATAWIDTH-1:0] data1 [DATADEPTH-1:0];
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(* keep, mem2reg *) reg [DATAWIDTH-1:0] data2 [DATADEPTH-1:0];
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endmodule
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EOT
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proc
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cd top
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2020-02-23 19:39:36 -06:00
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select -assert-count 1 m:data1 a:src=<<EOT:4.43-4.48 %i
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select -assert-count 2 w:data2[*] a:src=<<EOT:5.41-5.46 %i
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2019-08-22 18:57:59 -05:00
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select -assert-none a:mem2reg
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