mirror of https://github.com/YosysHQ/yosys.git
18 lines
516 B
Plaintext
18 lines
516 B
Plaintext
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# just so slightly adjust the example from check.ys to induce a loop
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design -reset
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read -vlog2k <<EOF
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module top(input clk, input a, input b, output [9:0] x);
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wire [9:0] ripple;
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reg [9:0] prev_ripple = 9'b0;
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always @(posedge clk) prev_ripple <= ripple;
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assign ripple = {ripple[8:1], a, ripple[0]} ^ prev_ripple;
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assign x = ripple[9] + b;
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endmodule
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EOF
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hierarchy -top top
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prep
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logger -expect warning "found logic loop in module top:" 1
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logger -expect error "Found 1 problems in 'check -assert'" 1
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check -assert
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