mirror of https://github.com/YosysHQ/yosys.git
13 lines
207 B
Plaintext
13 lines
207 B
Plaintext
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read_verilog <<EOT
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module test (
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input signed [1:0] n,
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output [3:0] dout
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);
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assign dout = n + 4'sd 4;
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endmodule
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EOT
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alumacc
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select -assert-count 1 t:$alu
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equiv_opt -assert opt -fine
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