mirror of https://github.com/YosysHQ/yosys.git
15 lines
280 B
Plaintext
15 lines
280 B
Plaintext
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read_verilog <<EOT
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(* whitebox *)
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module box(input a, output q);
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assign q = ~a;
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endmodule
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module top(input a, output q);
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box box_i(.a(a), .q(q));
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endmodule
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EOT
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select -assert-count 1 =box/t:$not
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blackbox =box
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select -assert-count 0 =A:whitebox
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select -assert-count 0 =box/t:$not
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