mirror of https://github.com/YosysHQ/yosys.git
34 lines
950 B
Verilog
34 lines
950 B
Verilog
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`timescale 1ns/10ps
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module svinterface_at_top_wrapper(
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input logic clk,
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input logic rst,
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output logic [21:0] outOther,
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input logic [1:0] sig,
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output logic [1:0] sig_out,
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input logic flip,
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output logic [15:0] passThrough,
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input logic interfaceInstanceAtTop_setting,
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output logic [2:0] interfaceInstanceAtTop_other_setting,
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output logic [1:0] interfaceInstanceAtTop_mysig_out,
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output logic [15:0] interfaceInstanceAtTop_passThrough,
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);
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TopModule u_dut (
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.clk(clk),
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.rst(rst),
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.outOther(outOther),
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.sig(sig),
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.flip(flip),
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.passThrough(passThrough),
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.\interfaceInstanceAtTop.setting(interfaceInstanceAtTop_setting),
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.\interfaceInstanceAtTop.other_setting(interfaceInstanceAtTop_other_setting),
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.\interfaceInstanceAtTop.mysig_out(interfaceInstanceAtTop_mysig_out),
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.\interfaceInstanceAtTop.passThrough(interfaceInstanceAtTop_passThrough),
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.sig_out(sig_out)
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);
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endmodule
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