mirror of https://github.com/YosysHQ/yosys.git
43 lines
421 B
Verilog
43 lines
421 B
Verilog
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`timescale 1ns/1ns
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module tb_dffe();
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reg clk = 0;
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reg en = 0;
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reg d = 0;
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wire q;
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dffe uut(.clk(clk),.d(d),.en(en),.q(q));
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always
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#(5) clk <= !clk;
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initial
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begin
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$dumpfile("tb_dffe");
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$dumpvars(0,tb_dffe);
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#10
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d = 1;
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#10
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d = 0;
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#10
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d = 1;
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#10
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d = 0;
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#10
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en = 1;
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#10
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d = 1;
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#10
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d = 0;
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#10
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d = 1;
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#10
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d = 0;
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#10
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d = 1;
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#10
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d = 0;
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#10
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$finish;
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end
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endmodule
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