yosys/tests/sim/sdff.v

8 lines
122 B
Verilog
Raw Permalink Normal View History

2022-02-15 02:35:53 -06:00
module sdff( input d, clk, rst, output reg q );
always @( posedge clk)
if (rst)
q <= 0;
else
q <= d;
endmodule