yosys/tests/sim/dlatchsr.v

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2022-02-16 06:58:51 -06:00
module dlatchsr( input d, set, clr, en, output reg q );
always @* begin
if ( clr )
q = 0;
else if (set)
q = 1;
else
if (en)
q = d;
end
endmodule