mirror of https://github.com/YosysHQ/yosys.git
30 lines
643 B
Verilog
30 lines
643 B
Verilog
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module RAM_WIDE_WRITE #(
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parameter [63:0] INIT = 64'hx,
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parameter PORT_A_RD_WIDTH = 2,
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parameter PORT_A_WR_WIDTH = 8,
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parameter PORT_A_WR_EN_WIDTH = 2
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) (
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input PORT_A_CLK,
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input PORT_A_RD_EN,
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input [5:0] PORT_A_ADDR,
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output reg [1:0] PORT_A_RD_DATA,
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input [1:0] PORT_A_WR_EN,
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input [7:0] PORT_A_WR_DATA
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);
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reg [63:0] mem;
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initial mem = INIT;
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always @(posedge PORT_A_CLK) begin
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if (PORT_A_RD_EN)
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PORT_A_RD_DATA <= mem[{PORT_A_ADDR[5:1],1'b0}+:2];
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if (PORT_A_WR_EN[0])
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mem[{PORT_A_ADDR[5:3],3'b000}+:4] <= PORT_A_WR_DATA[3:0];
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if (PORT_A_WR_EN[1])
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mem[{PORT_A_ADDR[5:3],3'b100}+:4] <= PORT_A_WR_DATA[7:4];
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end
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endmodule
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