mirror of https://github.com/YosysHQ/yosys.git
55 lines
1.9 KiB
Verilog
55 lines
1.9 KiB
Verilog
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module RAM_WIDE_SP #(
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parameter [79:0] INIT = 80'hx,
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parameter PORT_A_RD_WIDTH = 1,
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parameter PORT_A_WR_WIDTH = 1,
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parameter PORT_A_WIDTH = 1,
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parameter OPTION_WIDTH_MIX = 0,
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parameter PORT_A_WR_EN_WIDTH = 1,
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parameter PORT_A_RD_SRST_VALUE = 16'hx,
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parameter RD_WIDTH = OPTION_WIDTH_MIX ? PORT_A_RD_WIDTH : PORT_A_WIDTH,
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parameter WR_WIDTH = OPTION_WIDTH_MIX ? PORT_A_WR_WIDTH : PORT_A_WIDTH
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) (
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input PORT_A_CLK,
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input PORT_A_RD_EN,
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input PORT_A_RD_SRST,
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input [5:0] PORT_A_ADDR,
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output reg [RD_WIDTH-1:0] PORT_A_RD_DATA,
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input [PORT_A_WR_EN_WIDTH-1:0] PORT_A_WR_EN,
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input [WR_WIDTH-1:0] PORT_A_WR_DATA
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);
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reg [79:0] mem;
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initial mem = INIT;
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always @(posedge PORT_A_CLK)
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if (PORT_A_RD_SRST)
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PORT_A_RD_DATA <= PORT_A_RD_SRST_VALUE;
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else if (PORT_A_RD_EN)
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case (RD_WIDTH)
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1: PORT_A_RD_DATA <= mem[PORT_A_ADDR[5:2] * 5 + PORT_A_ADDR[1:0]+:1];
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2: PORT_A_RD_DATA <= mem[PORT_A_ADDR[5:2] * 5 + PORT_A_ADDR[1] * 2+:2];
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5: PORT_A_RD_DATA <= mem[PORT_A_ADDR[5:2] * 5+:5];
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10: PORT_A_RD_DATA <= mem[PORT_A_ADDR[5:3] * 10+:10];
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20: PORT_A_RD_DATA <= mem[PORT_A_ADDR[5:4] * 20+:20];
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endcase
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always @(posedge PORT_A_CLK)
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case (WR_WIDTH)
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1: if (PORT_A_WR_EN) mem[PORT_A_ADDR[5:2] * 5 + PORT_A_ADDR[1:0]+:1] <= PORT_A_WR_DATA;
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2: if (PORT_A_WR_EN) mem[PORT_A_ADDR[5:2] * 5 + PORT_A_ADDR[1] * 2+:2] <= PORT_A_WR_DATA;
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5: if (PORT_A_WR_EN) mem[PORT_A_ADDR[5:2] * 5+:5] <= PORT_A_WR_DATA;
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10: begin
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if (PORT_A_WR_EN[0]) mem[PORT_A_ADDR[5:3] * 10+:5] <= PORT_A_WR_DATA[4:0];
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if (PORT_A_WR_EN[1]) mem[PORT_A_ADDR[5:3] * 10 + 5+:5] <= PORT_A_WR_DATA[9:5];
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end
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20: begin
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if (PORT_A_WR_EN[0]) mem[PORT_A_ADDR[5:4] * 20+:5] <= PORT_A_WR_DATA[4:0];
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if (PORT_A_WR_EN[1]) mem[PORT_A_ADDR[5:4] * 20 + 5+:5] <= PORT_A_WR_DATA[9:5];
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if (PORT_A_WR_EN[2]) mem[PORT_A_ADDR[5:4] * 20 + 10+:5] <= PORT_A_WR_DATA[14:10];
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if (PORT_A_WR_EN[3]) mem[PORT_A_ADDR[5:4] * 20 + 15+:5] <= PORT_A_WR_DATA[19:15];
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end
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endcase
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endmodule
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