mirror of https://github.com/YosysHQ/yosys.git
82 lines
2.3 KiB
Verilog
82 lines
2.3 KiB
Verilog
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module RAM_BLOCK_SP(
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input PORT_A_CLK,
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input PORT_A_CLK_EN,
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input PORT_A_RD_EN,
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input PORT_A_RD_ARST,
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input PORT_A_RD_SRST,
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input [1:0] PORT_A_WR_EN,
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input [3:0] PORT_A_ADDR,
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output reg [15:0] PORT_A_RD_DATA,
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input [15:0] PORT_A_WR_DATA
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);
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parameter OPTION_RDWR = "UNDEFINED";
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parameter OPTION_RDINIT = "UNDEFINED";
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parameter OPTION_RDARST = "UNDEFINED";
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parameter OPTION_RDSRST = "UNDEFINED";
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parameter OPTION_SRST_GATE = 0;
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parameter PORT_A_RD_INIT_VALUE = 16'hxxxx;
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parameter PORT_A_RD_ARST_VALUE = 16'hxxxx;
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parameter PORT_A_RD_SRST_VALUE = 16'hxxxx;
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reg [15:0] mem [0:15];
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initial
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if (OPTION_RDINIT == "ZERO")
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PORT_A_RD_DATA = 0;
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else if (OPTION_RDINIT == "ANY")
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PORT_A_RD_DATA = PORT_A_RD_INIT_VALUE;
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localparam ARST_VALUE =
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(OPTION_RDARST == "ZERO") ? 16'h0000 :
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(OPTION_RDARST == "INIT") ? PORT_A_RD_INIT_VALUE :
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(OPTION_RDARST == "ANY") ? PORT_A_RD_ARST_VALUE :
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16'hxxxx;
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localparam SRST_VALUE =
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(OPTION_RDSRST == "ZERO") ? 16'h0000 :
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(OPTION_RDSRST == "INIT") ? PORT_A_RD_INIT_VALUE :
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(OPTION_RDSRST == "ANY") ? PORT_A_RD_SRST_VALUE :
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16'hxxxx;
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pullup (PORT_A_CLK_EN);
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pullup (PORT_A_RD_EN);
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pulldown (PORT_A_RD_ARST);
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pulldown (PORT_A_RD_SRST);
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always @(posedge PORT_A_CLK) begin
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if (PORT_A_CLK_EN) begin
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if (PORT_A_WR_EN[0])
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mem[PORT_A_ADDR][7:0] <= PORT_A_WR_DATA[7:0];
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if (PORT_A_WR_EN[1])
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mem[PORT_A_ADDR][15:8] <= PORT_A_WR_DATA[15:8];
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if (PORT_A_RD_EN && (!PORT_A_WR_EN || OPTION_RDWR != "NO_CHANGE")) begin
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PORT_A_RD_DATA <= mem[PORT_A_ADDR];
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if (PORT_A_WR_EN && OPTION_RDWR == "NEW_ONLY")
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PORT_A_RD_DATA <= 16'hx;
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if (PORT_A_WR_EN[0])
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case (OPTION_RDWR)
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"NEW": PORT_A_RD_DATA[7:0] <= PORT_A_WR_DATA[7:0];
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"NEW_ONLY": PORT_A_RD_DATA[7:0] <= PORT_A_WR_DATA[7:0];
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"UNDEFINED": PORT_A_RD_DATA[7:0] <= 8'hx;
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endcase
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if (PORT_A_WR_EN[1])
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case (OPTION_RDWR)
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"NEW": PORT_A_RD_DATA[15:8] <= PORT_A_WR_DATA[15:8];
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"NEW_ONLY": PORT_A_RD_DATA[15:8] <= PORT_A_WR_DATA[15:8];
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"UNDEFINED": PORT_A_RD_DATA[15:8] <= 8'hx;
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endcase
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end
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end
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if (PORT_A_RD_SRST && (!OPTION_SRST_GATE || (OPTION_SRST_GATE == 2 && PORT_A_RD_EN) || (OPTION_SRST_GATE == 1 && PORT_A_CLK_EN)))
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PORT_A_RD_DATA <= SRST_VALUE;
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end
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always @(PORT_A_RD_ARST)
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if (PORT_A_RD_ARST)
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force PORT_A_RD_DATA = ARST_VALUE;
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else
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release PORT_A_RD_DATA;
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endmodule
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