mirror of https://github.com/YosysHQ/yosys.git
24 lines
412 B
Verilog
24 lines
412 B
Verilog
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// A memory initialized with an external file
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module memory (
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input clk_i,
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input we_i,
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input [5:0] addr_i,
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input [31:0] data_i,
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output reg [31:0] data_o
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);
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parameter MEMFILE = "";
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reg [31:0] mem [0:63];
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initial $readmemb(MEMFILE,mem);
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always @(posedge clk_i) begin
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if (we_i)
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mem[addr_i] <= data_i;
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data_o <= mem[addr_i];
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end
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endmodule
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