mirror of https://github.com/YosysHQ/yosys.git
73 lines
1.9 KiB
Plaintext
73 lines
1.9 KiB
Plaintext
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/********************************************/
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/* */
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/* Supergate cell library for Bench marking */
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/* */
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/* Symbiotic EDA GmbH / Moseley Instruments */
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/* Niels A. Moseley */
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/* */
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/* Process: none */
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/* */
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/* Date : 24-03-2019 */
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/* Version: 1.0 */
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/* Version: 1.1 - Removed semicolons in */
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/* full adder */
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/* */
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/********************************************/
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/*
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semi colon is missing in full-adder specification
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some TSMC liberty files are formatted this way..
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*/
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library(supergate) {
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technology (cmos);
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revision : 1.0;
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time_unit : "1ps";
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pulling_resistance_unit : "1kohm";
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voltage_unit : "1V";
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current_unit : "1uA";
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capacitive_load_unit(1,ff);
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default_inout_pin_cap : 7.0;
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default_input_pin_cap : 7.0;
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default_output_pin_cap : 0.0;
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default_fanout_load : 1.0;
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default_wire_load_capacitance : 0.1;
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default_wire_load_resistance : 1.0e-3;
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default_wire_load_area : 0.0;
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nom_process : 1.0;
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nom_temperature : 25.0;
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nom_voltage : 1.2;
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delay_model : generic_cmos;
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/* full adder */
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cell (fulladder) {
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area : 8
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pin(A) {
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direction : input
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}
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pin(B) {
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direction : input
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}
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pin(CI) {
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direction : input
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}
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pin(CO) {
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direction : output
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function : "(((A * B)+(B * CI))+(CI * A))"
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}
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pin(Y) {
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direction: output
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function : "((A^B)^CI)"
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}
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}
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} /* end */
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