mirror of https://github.com/YosysHQ/yosys.git
82 lines
2.3 KiB
Plaintext
82 lines
2.3 KiB
Plaintext
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/********************************************/
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/* */
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/* Supergate cell library for Bench marking */
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/* */
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/* Symbiotic EDA GmbH / Moseley Instruments */
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/* Niels A. Moseley */
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/* */
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/* Process: none */
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/* */
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/* Date : 02-11-2018 */
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/* Version: 1.0 */
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/* */
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/********************************************/
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library(supergate) {
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technology (cmos);
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revision : 1.0;
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time_unit : "1ps";
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pulling_resistance_unit : "1kohm";
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voltage_unit : "1V";
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current_unit : "1uA";
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capacitive_load_unit(1,ff);
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default_inout_pin_cap : 7.0;
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default_input_pin_cap : 7.0;
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default_output_pin_cap : 0.0;
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default_fanout_load : 1.0;
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default_wire_load_capacitance : 0.1;
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default_wire_load_resistance : 1.0e-3;
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default_wire_load_area : 0.0;
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nom_process : 1.0;
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nom_temperature : 25.0;
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nom_voltage : 1.2;
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delay_model : generic_cmos;
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type( IO_bus_3_to_0 ) {
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base_type : array ;
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data_type : bit ;
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bit_width : 4;
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bit_from : 3 ;
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bit_to : 0 ;
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downto : true ;
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}
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cell (SRAM) {
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area : 1 ;
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memory() {
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type : ram;
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address_width : 4;
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word_width : 4;
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}
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pin(CE1) {
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direction : input;
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capacitance : 0.021;
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max_transition : 1.024;
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switch_pin : true;
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}
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bus(I1) {
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bus_type : IO_bus_3_to_0 ;
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direction : input;
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pin (I1[3:0]) {
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timing() {
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related_pin : "CE1" ;
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timing_type : setup_rising ;
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rise_constraint (scalar) {
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values("0.0507786");
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}
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fall_constraint (scalar) {
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values("0.0507786");
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}
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}
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}
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}
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}
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} /* end */
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