mirror of https://github.com/YosysHQ/yosys.git
21 lines
506 B
Verilog
21 lines
506 B
Verilog
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// test_simulation_xor_1_test.v
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module f1_test(input [1:0] in, output out);
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assign out = (in[0] ^ in[1]);
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endmodule
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// test_simulation_xor_2_test.v
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module f2_test(input [2:0] in, output out);
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assign out = (in[0] ^ in[1] ^ in[2]);
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endmodule
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// test_simulation_xor_3_test.v
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module f3_test(input [3:0] in, output out);
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assign out = (in[0] ^ in[1] ^ in[2] ^ in[3]);
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endmodule
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// test_simulation_xor_4_test.v
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module f4_test(input [3:0] in, output out);
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xor myxor(out, in[0], in[1], in[2], in[3]);
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endmodule
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