mirror of https://github.com/YosysHQ/yosys.git
31 lines
738 B
Verilog
31 lines
738 B
Verilog
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// test_simulation_or_1_test.v
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module f1_test(input [1:0] in, output out);
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assign out = in[0] | in[1];
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endmodule
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// test_simulation_or_2_test.v
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module f2_test(input [1:0] in, output out);
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assign out = in[0] || in[1];
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endmodule
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// test_simulation_or_3_test.v
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module f3_test(input [2:0] in, output out);
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assign out = in[0] | in[1] | in[2];
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endmodule
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// test_simulation_or_4_test.v
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module f4_test(input [2:0] in, output out);
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assign out = in[0] || in[1] || in[2];
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endmodule
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// test_simulation_or_5_test.v
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module f5_test(input [3:0] in, output out);
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assign out = in[0] | in[1] | in[2] | in[3];
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endmodule
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// test_simulation_or_6_test.v
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module f6_test(input [3:0] in, output out);
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assign out = in[0] || in[1] || in[2] || in[3];
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endmodule
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