mirror of https://github.com/YosysHQ/yosys.git
20 lines
262 B
Verilog
20 lines
262 B
Verilog
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module syn_reset (clk,reset,a,c);
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input clk;
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input reset;
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input a;
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output c;
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wire clk;
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wire reset;
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wire a;
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reg c;
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always @ (posedge clk )
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if ( reset == 1'b1) begin
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c <= 0;
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end else begin
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c <= a;
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end
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endmodule
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