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yosys/tests/arch/nexus/lutram.ys

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synth_nexus: Initial implementation Signed-off-by: David Shah <dave@ds0.me>
2020-10-01 05:15:54 -05:00
read_verilog ../common/lutram.v
hierarchy -top lutram_1w1r
proc
memory -nomap
equiv_opt -run :prove -map +/nexus/cells_sim.v synth_nexus
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd lutram_1w1r
stat
select -assert-count 8 t:WIDEFN9
memory_bram: Reuse extract_rdff helper for make_outreg. Also properly skip read ports with init value or reset when not making use of make_outreg. Proper support for matching those will land later.
2021-05-25 12:31:53 -05:00
select -assert-count 12 t:LUT4
synth_nexus: Initial implementation Signed-off-by: David Shah <dave@ds0.me>
2020-10-01 05:15:54 -05:00
select -assert-count 8 t:DPR16X4
memory_bram: Reuse extract_rdff helper for make_outreg. Also properly skip read ports with init value or reset when not making use of make_outreg. Proper support for matching those will land later.
2021-05-25 12:31:53 -05:00
select -assert-count 8 t:FD1P3IX
synth_nexus: Initial implementation Signed-off-by: David Shah <dave@ds0.me>
2020-10-01 05:15:54 -05:00
select -assert-none t:DPR16X4 t:FD1P3IX t:WIDEFN9 t:LUT4 t:INV t:IB t:OB t:VLO t:VHI %% t:* %D