mirror of https://github.com/YosysHQ/yosys.git
45 lines
1.7 KiB
Plaintext
45 lines
1.7 KiB
Plaintext
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read_verilog ../common/adffs.v
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design -save read
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hierarchy -top adff
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proc
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equiv_opt -async2sync -assert -map +/nexus/cells_sim.v synth_nexus # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd adff # Constrain all select calls below inside the top module
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stat
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select -assert-count 1 t:FD1P3DX
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select -assert-none t:FD1P3DX t:IB t:OB t:VLO t:VHI %% t:* %D
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design -load read
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hierarchy -top adffn
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proc
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equiv_opt -async2sync -assert -map +/nexus/cells_sim.v synth_nexus # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd adffn # Constrain all select calls below inside the top module
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stat
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select -assert-count 1 t:FD1P3DX
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select -assert-count 1 t:INV
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select -assert-none t:FD1P3DX t:INV t:LUT4 t:IB t:OB t:VLO t:VHI %% t:* %D
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design -load read
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hierarchy -top dffs
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proc
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equiv_opt -async2sync -assert -map +/nexus/cells_sim.v synth_nexus # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dffs # Constrain all select calls below inside the top module
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stat
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select -assert-count 1 t:FD1P3IX
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select -assert-count 1 t:LUT4
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select -assert-none t:FD1P3IX t:LUT4 t:IB t:OB t:VLO t:VHI %% t:* %D
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design -load read
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hierarchy -top ndffnr
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proc
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equiv_opt -async2sync -assert -map +/nexus/cells_sim.v synth_nexus # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd ndffnr # Constrain all select calls below inside the top module
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stat
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select -assert-count 1 t:FD1P3IX
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select -assert-count 2 t:INV
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select -assert-none t:FD1P3IX t:INV t:LUT4 t:IB t:OB t:VLO t:VHI %% t:* %D
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