mirror of https://github.com/YosysHQ/yosys.git
16 lines
407 B
Plaintext
16 lines
407 B
Plaintext
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read_verilog spram.v
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hierarchy -top top
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synth_ice40
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select -assert-count 1 t:SB_SPRAM256KA
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select -assert-none t:SB_SPRAM256KA %% t:* %D
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# Testing with pattern as described in pattern document
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design -reset
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read_verilog spram.v
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chparam -set SKIP_RDEN 0
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hierarchy -top top
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synth_ice40
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select -assert-count 1 t:SB_SPRAM256KA
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# Below fails due to extra SB_LUT4
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# select -assert-none t:SB_SPRAM256KA %% t:* %D
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