yosys/tests/arch/gatemate/latches.ys

read_verilog ../common/latches.v
design -save read

hierarchy -top latchp
proc
equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd latchp # Constrain all select calls below inside the top module
select -assert-count 1 t:CC_DLT
select -assert-none t:CC_DLT %% t:* %D

design -load read
hierarchy -top latchn
proc
equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd latchn # Constrain all select calls below inside the top module
select -assert-count 1 t:CC_DLT
select -assert-none t:CC_DLT %% t:* %D

design -load read
hierarchy -top latchsr
proc
equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd latchsr # Constrain all select calls below inside the top module
select -assert-count 1 t:CC_DLT
select -assert-max 2 t:CC_LUT3
select -assert-none t:CC_DLT t:CC_LUT3 %% t:* %D