mirror of https://github.com/YosysHQ/yosys.git
8 lines
268 B
Plaintext
8 lines
268 B
Plaintext
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read_verilog -icells <<EOF
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module top(input c, r, input [1:0] d, output reg [1:0] q);
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TRELLIS_FF #(.REGSET("SET")) ff1(.CLK(c), .LSR(r), .DI(d[0]), .Q(q[0]));
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TRELLIS_FF #(.REGSET("SET")) ff2(.CLK(c), .LSR(r), .DI(d[1]), .Q(q[1]));
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endmodule
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EOF
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synth_ecp5 -abc9 -dff
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