yosys/docs/source/cell/word_reg.rst

.. role:: verilog(code)
   :language: Verilog

Registers
---------

SR-type latches are represented by `$sr` cells. These cells have input ports
``SET`` and ``CLR`` and an output port ``Q``. They have the following
parameters:

``WIDTH``
   The width of inputs ``SET`` and ``CLR`` and output ``Q``.

``SET_POLARITY``
   The set input bits are active-high if this parameter has the value ``1'b1``
   and active-low if this parameter is ``1'b0``.

``CLR_POLARITY``
   The reset input bits are active-high if this parameter has the value ``1'b1``
   and active-low if this parameter is ``1'b0``.

Both set and reset inputs have separate bits for every output bit. When both the
set and reset inputs of an `$sr` cell are active for a given bit index, the
reset input takes precedence.

D-type flip-flops are represented by `$dff` cells. These cells have a clock port
``CLK``, an input port ``D`` and an output port ``Q``. The following parameters
are available for `$dff` cells:

``WIDTH``
   The width of input ``D`` and output ``Q``.

``CLK_POLARITY``
   Clock is active on the positive edge if this parameter has the value ``1'b1``
   and on the negative edge if this parameter is ``1'b0``.

D-type flip-flops with asynchronous reset are represented by `$adff` cells. As
the `$dff` cells they have ``CLK``, ``D`` and ``Q`` ports. In addition they also
have a single-bit ``ARST`` input port for the reset pin and the following
additional two parameters:

``ARST_POLARITY``
   The asynchronous reset is active-high if this parameter has the value
   ``1'b1`` and active-low if this parameter is ``1'b0``.

``ARST_VALUE``
      The state of ``Q`` will be set to this value when the reset is active.

Usually these cells are generated by the `proc` pass using the information in
the designs RTLIL::Process objects.

D-type flip-flops with synchronous reset are represented by `$sdff` cells. As
the `$dff` cells they have ``CLK``, ``D`` and ``Q`` ports. In addition they also
have a single-bit ``SRST`` input port for the reset pin and the following
additional two parameters:

``SRST_POLARITY``
   The synchronous reset is active-high if this parameter has the value ``1'b1``
   and active-low if this parameter is ``1'b0``.

``SRST_VALUE``
   The state of ``Q`` will be set to this value when the reset is active.

Note that the `$adff` and `$sdff` cells can only be used when the reset value is
constant.

D-type flip-flops with asynchronous load are represented by `$aldff` cells. As
the `$dff` cells they have ``CLK``, ``D`` and ``Q`` ports. In addition they also
have a single-bit ``ALOAD`` input port for the async load enable pin, a ``AD``
input port with the same width as data for the async load data, and the
following additional parameter:

``ALOAD_POLARITY``
   The asynchronous load is active-high if this parameter has the value ``1'b1``
   and active-low if this parameter is ``1'b0``.

D-type flip-flops with asynchronous set and reset are represented by `$dffsr`
cells. As the `$dff` cells they have ``CLK``, ``D`` and ``Q`` ports. In addition
they also have multi-bit ``SET`` and ``CLR`` input ports and the corresponding
polarity parameters, like `$sr` cells.

D-type flip-flops with enable are represented by `$dffe`, `$adffe`, `$aldffe`,
`$dffsre`, `$sdffe`, and `$sdffce` cells, which are enhanced variants of `$dff`,
`$adff`, `$aldff`, `$dffsr`, `$sdff` (with reset over enable) and `$sdff` (with
enable over reset) cells, respectively.  They have the same ports and parameters
as their base cell. In addition they also have a single-bit ``EN`` input port
for the enable pin and the following parameter:

``EN_POLARITY``
   The enable input is active-high if this parameter has the value ``1'b1`` and
   active-low if this parameter is ``1'b0``.

D-type latches are represented by `$dlatch` cells.  These cells have an enable
port ``EN``, an input port ``D``, and an output port ``Q``.  The following
parameters are available for `$dlatch` cells:

``WIDTH``
   The width of input ``D`` and output ``Q``.

``EN_POLARITY``
   The enable input is active-high if this parameter has the value ``1'b1`` and
   active-low if this parameter is ``1'b0``.

The latch is transparent when the ``EN`` input is active.

D-type latches with reset are represented by `$adlatch` cells.  In addition to
`$dlatch` ports and parameters, they also have a single-bit ``ARST`` input port
for the reset pin and the following additional parameters:

``ARST_POLARITY``
   The asynchronous reset is active-high if this parameter has the value
   ``1'b1`` and active-low if this parameter is ``1'b0``.

``ARST_VALUE``
   The state of ``Q`` will be set to this value when the reset is active.

D-type latches with set and reset are represented by `$dlatchsr` cells. In
addition to `$dlatch` ports and parameters, they also have multi-bit ``SET`` and
``CLR`` input ports and the corresponding polarity parameters, like `$sr` cells.

.. autocellgroup:: reg
   :members:
   :source:
   :linenos: