yosys/tests/verilog/struct_access.ys

read_verilog -formal -sv struct_access.sv
proc
opt -full
async2sync
sat -verify -seq 1 -prove-asserts -show-all
sv: fix two struct access bugs - preserve signedness of struct members - fix initial width detection of struct members (e.g., in case expressions) 2021-06-22 09:39:57 -05:00			`read_verilog -formal -sv struct_access.sv`
			`proc`
			`opt -full`
tests: Run async2sync before sat and/or sim to handle $check cells Right now neither `sat` nor `sim` have support for the `$check` cell. For formal verification it is a good idea to always run either async2sync or clk2fflogic which will (in a future commit) lower `$check` to `$assert`, etc. While `sim` should eventually support `$check` directly, using `async2sync` is ok for the current tests that use `sim`, so this commit also runs `async2sync` before running sim on designs containing assertions. 2024-01-22 10:44:05 -06:00			`async2sync`
sv: fix two struct access bugs - preserve signedness of struct members - fix initial width detection of struct members (e.g., in case expressions) 2021-06-22 09:39:57 -05:00			`sat -verify -seq 1 -prove-asserts -show-all`