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53 lines
1.0 KiB
Systemverilog
53 lines
1.0 KiB
Systemverilog
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module example #(
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parameter w,
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parameter x = 1,
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parameter byte y,
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parameter byte z = 3
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) (
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output a, b,
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output byte c, d
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);
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assign a = w;
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assign b = x;
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assign c = y;
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assign d = z;
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endmodule
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module top;
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wire a1, b1;
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wire a2, b2;
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wire a3, b3;
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wire a4, b4;
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byte c1, d1;
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byte c2, d2;
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byte c3, d3;
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byte c4, d4;
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example #(0, 1, 2) e1(a1, b1, c1, d1);
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example #(.w(1), .y(4)) e2(a2, b2, c2, d2);
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example #(.x(0), .w(1), .y(5)) e3(a3, b3, c3, d3);
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example #(1, 0, 9, 10) e4(a4, b4, c4, d4);
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always @* begin
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assert (a1 == 0);
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assert (b1 == 1);
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assert (c1 == 2);
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assert (d1 == 3);
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assert (a2 == 1);
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assert (b2 == 1);
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assert (c2 == 4);
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assert (d3 == 3);
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assert (a3 == 1);
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assert (b3 == 0);
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assert (c3 == 5);
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assert (d3 == 3);
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assert (a4 == 1);
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assert (b4 == 0);
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assert (c4 == 9);
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assert (d4 == 10);
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end
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endmodule
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