mirror of https://github.com/YosysHQ/yosys.git
16 lines
267 B
Plaintext
16 lines
267 B
Plaintext
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read_verilog -sv <<EOF
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module top;
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logic x;
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always_comb begin
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logic y;
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if (x)
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x = 1;
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else
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y = 1;
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x = y;
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end
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endmodule
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EOF
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logger -expect error "^Latch inferred for signal `\\top\.\$unnamed_block\$1\.y' from always_comb process" 1
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proc
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