mirror of https://github.com/YosysHQ/yosys.git
38 lines
757 B
Systemverilog
38 lines
757 B
Systemverilog
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typedef enum {
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WA, WB, WC, WD
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} wide_state_t;
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typedef enum logic [1:0] {
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A = 3, B = 0, C, D
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} state_t;
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module top(input clk, output z);
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wide_state_t wide_state = WA;
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always @(posedge clk) begin
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case (wide_state)
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WA: wide_state <= WB;
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WB: wide_state <= WC;
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WC: wide_state <= WD;
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default: wide_state <= WA;
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endcase
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end
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(* some_attribute = shortint'(42) *)
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(* another_attribute = -1 *)
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state_t state = A;
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always @(posedge clk) begin
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case (state)
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A: state <= B;
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B: state <= C;
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C: state <= D;
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default: state <= A;
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endcase
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end
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assign z = (wide_state == WB) ^ (state == B);
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endmodule
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