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yosys/tests/various/sv_defines.ys

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Add support for SystemVerilog-style `define to Verilog frontend This patch should support things like `define foo(a, b = 3, c) a+b+c `foo(1, ,2) which will evaluate to 1+3+2. It also spots mistakes like `foo(1) (the 3rd argument doesn't have a default value, so a call site is required to set it). Most of the patch is a simple parser for the format in preproc.cc, but I've also taken the opportunity to wrap up the "name -> definition" map in a type, rather than use multiple std::map's. Since this type needs to be visible to code that touches defines, I've pulled it (and the frontend_verilog_preproc declaration) out into a new file at frontends/verilog/preproc.h and included that where necessary. Finally, the patch adds a few tests in tests/various to check that we are parsing everything correctly.
2020-03-17 04:34:31 -05:00
# Check that basic macro expansions do what you'd expect
read_verilog <<EOT
`define empty_arglist() 123
`define one_arg(x) 123+x
`define opt_arg(x = 1) 123+x
`define two_args(x, y = (1+23)) x+y
`define nested_comma(x = {31'b0, 1'b1}, y=3) x+y
module top;
localparam a = `empty_arglist();
localparam b = `one_arg(10);
localparam c = `opt_arg(10);
localparam d = `opt_arg();
localparam e = `two_args(1,2);
localparam f = `two_args(1);
localparam g = `nested_comma(1, 2);
localparam h = `nested_comma({31'b0, (1'b0)});
localparam i = `nested_comma(, 1);
generate
if (a != 123) $error("a bad");
if (b != 133) $error("b bad");
if (c != 133) $error("c bad");
if (d != 124) $error("d bad");
if (e != 3) $error("e bad");
if (f != 25) $error("f bad");
if (g != 3) $error("g bad");
if (h != 3) $error("h bad");
if (i != 2) $error("i bad");
endgenerate
endmodule
EOT