mirror of https://github.com/YosysHQ/yosys.git
22 lines
474 B
Verilog
22 lines
474 B
Verilog
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`define DATA 64'h492e5c4d7747e032
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`define GATE(n, expr) \
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module gate``n(sel, out); \
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input wire [3:0] sel; \
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output wire out; \
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reg [63:0] bits; \
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reg [5:0] ptrs[15:0]; \
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initial bits = `DATA; \
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initial $readmemh("memory_word_as_index.data", ptrs); \
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assign out = expr; \
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endmodule
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`GATE(1, bits[ptrs[sel]])
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`GATE(2, bits[ptrs[sel][5:0]])
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`GATE(3, bits[ptrs[sel]+:1])
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module gold(sel, out);
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input wire [3:0] sel;
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output wire out = `DATA >> (sel * 4);
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endmodule
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