mirror of https://github.com/YosysHQ/yosys.git
24 lines
305 B
Plaintext
24 lines
305 B
Plaintext
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read_verilog <<EOT
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module bb (...);
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parameter A = "abc";
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parameter B = 1;
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parameter C = 2;
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input a;
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output b;
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endmodule
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module top (...);
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input a;
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output b;
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bb #("def", 3) my_bb (a, b);
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endmodule
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EOT
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hierarchy -top top
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dump
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select -assert-count 1 t:bb r:A=def %i
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select -assert-count 1 t:bb r:B=3 %i
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