mirror of https://github.com/YosysHQ/yosys.git
19 lines
283 B
Plaintext
19 lines
283 B
Plaintext
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read_verilog -sv <<EOT
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parameter A = 10;
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parameter B = A;
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typedef enum {
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CONST_A = A,
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CONST_B = A+1
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} enum_t;
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module top(output [3:0] q, output [3:0] r);
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assign q = 10;
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assign r = CONST_B;
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endmodule
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EOT
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hierarchy -top top
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sat -verify -prove q 10 top
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sat -verify -prove r 11 top
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