yosys/tests/various/fib_tern.ys

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read_verilog fib_tern.v
hierarchy
proc
equiv_make gold gate equiv
equiv_simple
equiv_status -assert
verilog: support recursive functions using ternary expressions This adds a mechanism for marking certain portions of elaboration as occurring within unevaluated ternary branches. To enable elaboration of the overall ternary, this also adds width detection for these unelaborated function calls. 2021-02-12 13:25:34 -06:00			`read_verilog fib_tern.v`
			`hierarchy`
			`proc`
			`equiv_make gold gate equiv`
			`equiv_simple`
			`equiv_status -assert`