mirror of https://github.com/YosysHQ/yosys.git
13 lines
217 B
Plaintext
13 lines
217 B
Plaintext
|
read_verilog <<EOT
|
||
|
|
module top(input clk, pre, d, output reg q);
|
||
|
|
always @(posedge clk, posedge pre)
|
||
|
|
if (pre)
|
||
|
|
q <= 1'b1;
|
||
|
|
else
|
||
|
|
q <= d;
|
||
|
|
endmodule
|
||
|
|
EOT
|
||
|
|
|
||
|
|
prep
|
||
|
|
equiv_opt -assert -multiclock -map +/simcells.v synth
|