mirror of https://github.com/YosysHQ/yosys.git
19 lines
497 B
Verilog
19 lines
497 B
Verilog
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`default_nettype none
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module latch_002_gate(dword, vect, sel, st);
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output reg [63:0] dword;
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input wire [7:0] vect;
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input wire [7:0] sel;
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input wire st;
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reg [63:0] mask;
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reg [63:0] data;
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always @*
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case (|(st))
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1'b 1:
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begin
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mask = (8'b 11111111)<<((((8)*(sel)))+(0));
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data = ((8'b 11111111)&(vect[7:0]))<<((((8)*(sel)))+(0));
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dword <= ((dword)&(~(mask)))|(data);
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end
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endcase
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endmodule
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