mirror of https://github.com/YosysHQ/yosys.git
34 lines
440 B
Plaintext
34 lines
440 B
Plaintext
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read_verilog <<EOT
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module top(input clk, input rst);
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reg [1:0] state;
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always @(posedge clk, posedge rst) begin
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if (rst)
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state <= 0;
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else
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case (state)
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2'b00: state <= 2'b01;
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2'b01: state <= 2'b10;
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2'b10: state <= 2'b00;
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endcase
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end
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sub sub_i(.i(state == 0));
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endmodule
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(* blackbox, keep *)
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module sub(input i);
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endmodule
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EOT
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proc
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fsm
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# Make sure there is a driver
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select -assert-any t:sub %ci %a w:* %i %ci c:* %i
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