mirror of https://github.com/YosysHQ/yosys.git
10 lines
183 B
Verilog
10 lines
183 B
Verilog
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module dffsr( input clk, d, clr, set, output reg q );
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always @( posedge clk, posedge set, posedge clr)
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if ( clr )
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q <= 0;
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else if (set)
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q <= 1;
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else
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q <= d;
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endmodule
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