mirror of https://github.com/YosysHQ/yosys.git
14 lines
158 B
Plaintext
14 lines
158 B
Plaintext
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read_verilog <<EOF
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module top1;
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(* foo *)
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wire w;
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endmodule
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module top2;
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(* bar *)
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wire w;
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endmodule
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EOF
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logger -expect log top1 1
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select -list-mod a:foo %m
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