mirror of https://github.com/YosysHQ/yosys.git
34 lines
669 B
Verilog
34 lines
669 B
Verilog
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module test1(input clk, input [3:0] a, output reg [3:0] y);
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always @(posedge clk)
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y <= a;
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endmodule
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module test2(input clk, input [3:0] a, output reg [3:0] y);
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wire clk_n = !clk;
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always @(negedge clk_n)
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y[1:0] <= a[1:0];
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always @(negedge clk_n)
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y[3:2] <= a[3:2];
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endmodule
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// -----------------------------------------------------------
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module test3(input clk, rst, input [3:0] a, output reg [3:0] y);
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always @(posedge clk, posedge rst)
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if (rst)
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y <= 12;
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else
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y <= |a;
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endmodule
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module test4(input clk, rst, input [3:0] a, output reg [3:0] y);
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wire rst_n = !rst;
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always @(posedge clk, negedge rst_n)
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if (!rst_n)
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y <= 12;
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else
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y <= a != 0;
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endmodule
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