mirror of https://github.com/YosysHQ/yosys.git
28 lines
342 B
Plaintext
28 lines
342 B
Plaintext
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read_verilog <<EOT
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module top(...);
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input [3:0] A, B, C;
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input S;
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input [1:0] T;
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output [3:0] X;
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output reg [3:0] Y;
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wire [3:0] D = A + B;
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assign X = S ? D : A + C;
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always @* begin
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case(T)
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2'b01: Y <= A;
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2'b10: Y <= B;
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default: Y <= D;
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endcase
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end
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endmodule
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EOT
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proc
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equiv_opt -assert opt_share
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