yosys/tests/memlib/memlib_block_sdp.txt

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2022-05-06 09:30:56 -05:00
ram block \RAM_BLOCK_SDP {
cost 64;
abits 10;
widths 1 2 4 8 16 per_port;
init any;
port sw "W" {
clock anyedge;
}
port sr "R" {
clock anyedge;
}
}