mirror of https://github.com/YosysHQ/yosys.git
25 lines
719 B
Verilog
25 lines
719 B
Verilog
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module top(input clk);
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reg a = 0;
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reg b = 0;
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wire y;
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sub s (.a(a), .b(b), .y(y));
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always @(posedge clk) begin
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a <= (!a && !b) || (a && !b);
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b <= (a && !b) || (a && b);
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end
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endmodule
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module sub(input a, input b, output wire y);
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assign y = a & b;
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// Not fit for our purposes: always @* if (a) $display(a, b, y);
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//
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// We compare output against iverilog, but async iverilog $display fires
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// even before values have propagated -- i.e. combinations of a/b/y will be
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// shown where a & b are both 1, but y has not yet taken the value 1. We
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// don't, so we specify it in the conditional.
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always @* if (y & (y == (a & b))) $display(a, b, y);
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endmodule
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