mirror of https://github.com/YosysHQ/yosys.git
25 lines
404 B
Verilog
25 lines
404 B
Verilog
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(* cxxrtl_blackbox *)
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module blackbox(...);
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(* cxxrtl_edge = "p" *)
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input clk;
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(* cxxrtl_sync *)
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output [7:0] out1;
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(* cxxrtl_sync *)
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output [7:0] out2;
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endmodule
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module unconnected_output(
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input clk,
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in,
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output out
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);
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blackbox bb (
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.clock (clock),
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.in (in),
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.out1 (out),
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.out2 (/* unconnected */),
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);
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endmodule
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