mirror of https://github.com/YosysHQ/yosys.git
26 lines
364 B
Verilog
26 lines
364 B
Verilog
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/* This is a
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Multi line comment
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example */
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module addbit (
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a,
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b,
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ci,
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sum,
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co);
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// Input Ports Single line comment
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input a;
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input b;
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input ci;
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// Output ports
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output sum;
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output co;
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// Data Types
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wire a;
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wire b;
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wire ci;
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wire sum;
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wire co;
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endmodule
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